View AD9054BST-135_660195.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9054 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 8-bit, 200 msps a/d converter functional block diagram encode timing encode ad9054 t/h ain ain gnd 1 2.5v reference 8 8 encode logic demultiplexer v dd ds ds demux quantizer vref in vref out da 7 Cda 0 db 7 Cdb 0 features 200 msps guaranteed conversion rate 135 msps low cost version available 350 mhz analog bandwidth 1 v p-p analog input range internal +2.5 v reference and t/h low power: 500 mw +5 v single supply operation ttl output interface single or demultiplexed output ports applications rgb graphics processing high resolution video digital data storage read channels digital communications digital instrumentation medical imaging general description the ad9054 is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. with a 200 msps encode rate capability and full-power analog bandwidth of 350 mhz, the component is ideal for applications requiring the highest possible dynamic performance. to minimize system cost and power dissipation, the ad9054 includes an internal +2.5 v reference and track-and-hold circuit. the user provides only a +5 v power supply and an encode clock. no external reference or driver components are required for many applications. the ad9054s encode input interfaces directly to ttl, cmos or positive-ecl logic and will operate with single-ended or differential inputs. the user may select dual-channel or single- channel digital outputs. the dual (demultiplexed) mode inter- leaves adc data through two 8-bit channels at one-half the clock rate. operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the adc to be clocked to the full 200 msps conversion rate. in the single- channel (nondemultiplexed) mode, all data is piped at the full clock rate to the channel a outputs. fabricated with an advanced bicmos process, the ad9054 is provided in a space-saving 44-lead tqfp surface mount plastic package (st-44) and specified over the full industrial (C40 c to +85 c) temperature range.
C2C rev. 0 ad9054Cspecifications electrical characteristics (v dd = +5 v, external reference, f s = max unless otherwise noted) test ad9054bst-200 AD9054BST-135 parameter temp level min typ max min typ max units resolution 8 8 bits dc accuracy differential nonlinearity +25 ci 0.9 +1.5/C1.0 0.9 +1.5/C1.0 lsb full vi 1.0 +2.0/C1.0 1.0 +2.0/C1.0 lsb integral nonlinearity +25 ci 0.6 1.5 0.6 1.5 lsb full vi 0.9 2.0 0.9 2.0 lsb no missing codes full vi guaranteed guaranteed gain error 1 +25 ci 2 7 2 7% fs gain tempco 1 full v 160 160 ppm/ c analog input input voltage range (with respect to ain ) full v 512 512 mv pCp compliance range ain or ain full v 1.8 3.2 1.8 3.2 v input offset voltage +25 ci 4 16 4 16 mv full vi 8 19 8 19 mv input resistance +25 c i 36 62 36 62 k w full vi 23 23 k w input capacitance +25 cv 4 4 pf input bias current +25 c i 25 50 25 50 m a full vi 75 75 m a analog bandwidth, full power 2 +25 c v 350 350 mhz reference output output voltage full vi 2.4 2.5 2.6 2.4 2.5 2.6 v temperature coefficient full v 110 110 ppm/ c switching performance maximum conversion rate (f s ) full vi 200 135 msps minimum conversion rate (f s ) full iv 25 25 msps encode pulsewidth high (t eh ) +25 c iv 2.0 15 3.0 15 ns encode pulsewidth low (t el ) +25 c iv 2.0 15 3.0 15 ns aperture delay (t a ) +25 c v 0.5 0.5 ns aperture uncertainty (jitter) +25 c v 2.3 2.3 ps rms data sync setup time (t sds ) +25 civ 0 0 ns data sync hold time (t hds ) +25 c iv 0.5 0.5 ns data sync pulsewidth (t pwds ) +25 c iv 2.0 2.0 ns output valid time (t v ) 3 full vi 2.7 5.1 2.7 5.7 ns output propagation delay (t pd ) 3 full vi 5.9 7.9 7.5 8.5 ns digital inputs high level current (i ih ) 4 full vi 500 625 500 625 m a low level current (i il ) 4 full vi 500 625 500 625 m a input capacitance +25 cv 3 3 pf differential inputs differential signal amplitude (v id ) full iv 400 400 mv high input voltage (v ihd ) full iv 1.5 v dd 1.5 v dd v low input voltage (v ild ) full iv 0 v dd C 0.4 0 v dd C 0.4 v common-mode input (v icm ) full iv 1.5 1.5 v demux input high input voltage (v ih ) full iv 2.0 v dd 2.0 v dd v low input voltage (v il ) full iv 0 0.8 0 0.8 v digital outputs high input voltage (v oh ) full vi 2.4 2.4 v low input voltage (v ol ) full vi 0.4 0.4 v output coding binary binary
C3C rev. 0 ad9054 test ad9054bst-200 AD9054BST-135 parameter temp level min typ max min typ max units power supply v dd supply current (i dd ) full vi 100 145 100 140 ma power dissipation 5, 6 full vi 500 725 500 700 mw power supply sensitivity 7 +25 c i 0.005 0.015 0.005 0.015 v/v dynamic performance 8 transient response +25 c v 1.5 1.5 ns overvoltage recovery time +25 c v 1.5 1.5 ns signal-to-noise ratio (snr) (without harmonics) f in = 19.7 mhz +25 civ 42 45 42 45 db full v 45 45 db f in = 49.7 mhz +25 c i 42 45 42 45 db full v 45 45 db f in = 70.1 mhz +25 c i 42 45 db full v 45 db signal-to-noise ratio (sinad) (with harmonics) f in = 19.7 mhz +25 civ 40 43 40 43 db full v 43 43 db f in = 49.7 mhz +25 c i 40 43 40 43 db full v 43 43 db f in = 70.1 mhz +25 c i 39 42 db full v 42 db effective number of bits f in = 19.7 mhz +25 c iv 6.35 6.85 6.35 6.85 bits f in = 49.7 mhz +25 c i 6.35 6.85 6.35 6.85 bits f in = 70.1 mhz +25 c i 6.18 6.85 bits 2nd harmonic distortion f in = 19.7 mhz +25 c iv 58 63 58 63 dbc f in = 49.7 mhz +25 c i 54 59 54 59 dbc f in = 70.1 mhz +25 c i 52 55 dbc 3rd harmonic distortion f in = 19.7 mhz +25 c iv 48 56 48 56 dbc f in = 49.7 mhz +25 c i 48 54 48 54 dbc f in = 70.1 mhz +25 c i 43 50 dbc two-tone intermod distortion (imd) f in = 19.7 mhz +25 c v 60 60 dbc f in = 49.7 mhz +25 c v 55 55 dbc f in = 70.1 mhz +25 c v 50 dbc notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed +2.5 v external reference). 2 3 db bandwidth with full-power input signal. 3 t v and t pd are measured from the threshold crossing of the encode input to valid ttl levels of the digital outputs. the output ac load du ring test is 5 pf (refer to equivalent circuits figures 5 and 6). 4 i ih and i il are valid for differential input voltages of less than 1.5 v. at higher differential voltages, the input current will increase to a maximum of 1.25 ma. 5 power dissipation is measured under the following conditions: analog input is C1 dbfs at 19.7 mhz. 6 typical thermal impedance for the st-44 (tqfp) 44Clead package (in still air): q jc = 20 c/w, q ca = 35 c/w, q ja = 55 c/w. 7 a change in input offset voltage with respect to a change in v dd . 8 snr/harmonics based on an analog input voltage of C1.0 dbfs referenced to a 1.024 v fullCscale input range. specifications subject to change without notice. explanation of test levels test level i. 100% production tested. ii. 100% production tested at +25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at +25 c; guaranteed by design and characterization testing for industrial temperature range.
ad9054 C4C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9054 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . v dd to 0.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . v dd to 0.0 v vref in, vref out . . . . . . . . . . . . . . . . . . . v dd to 0.0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . +175 c maximum case temperature . . . . . . . . . . . . . . . . . . +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. table i. output coding step ainC ain code binary 255 3 0.512 v 255 1111 1111 254 0.508 v 254 1111 1110 253 0.504 v 253 1111 1101 129 0.006 v 129 1000 0001 128 0.002 v 128 1000 0000 127 C0.002 v 127 0111 1111 126 C0.006 v 126 0111 1110 2 C0.504 v 2 0000 0010 1 C0.508 v 1 0000 0001 0 C0.512 v 0 0000 0000 ordering guide temperature package model range option* ad9054bst-200 C40 c to +85 c st-44 AD9054BST-135 C40 c to +85 c st-44 ad9054/pcb +25 c evaluation board *st = plastic thin quad flatpack (tqfp). pin function descriptions pin number name function 1 encode encode clock for adc (adc samples on rising edge of encode). 2 encode encode clock complement (adc samples on falling edge of encode ). 3, 5, 15, 18, 28, vdd power supply (+5 v). 30, 31, 36, 41 4, 6, 16, 17, 27, gnd ground. 29, 32, 35, 37, 40 14C7 da 0 Cda 7 digital outputs of adc channel a. da 7 is the msb, da 0 the lsb. 19C26 db 0 Cdb 7 digital outputs of adc channel b. db 7 is the msb, db 0 the lsb. 33 vref out internal reference output (+2.5 v typical); bypass with 0.1 m f to ground. 34 vref in refe rence input for adc (+2.5 v typical, 4%). 38 ain analog inputcomplement. connect to input signal midscale reference. 39 ain analog inputtrue. 42 demux format select. low = dual. channel mode, high = single. channel mode (channel a only). 43 ds data sync complement. 44 ds data syncaligns output chan- nels in dual-channel mode. pin configuration warning! esd sensitive device pin 1 identifier top view (pins down) db 1 db 2 db 3 gnd da 2 da 1 da 0 (lsb) vdd gnd vdd db 0 (lsb) vref out gnd vdd vdd gnd vdd gnd encode encode vdd gnd vdd gnd da 7 (msb) da 6 da 5 da 4 da 3 db 7 (msb) db 6 db 5 db 4 ds ds demux vdd gnd ain ain gnd vdd gnd vref in ad9054
ad9054 C5C rev. 0 ain d 7 Cd 0 encode encode sample nC1 sample n sample n+3 sample n+4 sample n+2 sample n+1 t a t eh t el 1/f s t pd t v data n data nC1 data nC2 data nC3 data nC4 data nC5 figure 1. timingsingle channel mode ain encode encode ds ds port a d 7 Cd 0 port b d 7 Cd 0 data nC7 or nC8 data nC7 or nC6 invalid if out of sync data nC4 if in sync data nC2 data n data nC8 or nC7 data nC6 or nC7 invalid if out of sync data nC5 if in sync data nC3 data nC1 data n+1 sample n+6 sample n+2 sample n+1 sample nC2 sample nC1 sample n sample n+3 sample n+4 sample n+5 t v t pd t pwds t sds t hds t sds t hds t eh t el 1/f s t a figure 2. timingdual channel mode
ad9054 C6C rev. 0 equivalent circuits v dd ain ain figure 3. equivalent analog input circuit v dd vref in figure 4. equivalent reference input circuit encode or ds 300 v 7.5k v 300 v 17.5k v v dd encode or ds figure 5. equivalent encode and data select input circuit demux v dd 300 v 300 v 17.5k v 7.5k v figure 6. equivalent demux input circuit v dd digital outputs figure 7. equivalent digital output circuit v dd vref out figure 8. equivalent reference output circuit
ad9054 C7C rev. 0 f in C mhz db 55 50 30 0 140 20 40 60 80 100 120 45 40 35 snr sinad nyquist frequency (100mhz) figure 9. snr vs. f in :f s = 200 msps f s C msps db 50 40 25 50 100 150 200 250 300 49 44 43 42 41 47 45 48 46 75 125 175 225 270 snr sinad figure 10. snr vs. f s : f in = 19.7 mhz f s C msps db 50 40 25 50 100 150 200 250 300 35 30 25 20 45 snr sinad 75 125 175 225 270 figure 11. snr vs. f s :f in = 70.1 mhz typical performance characteristicsC db t c C 8 c 44.0 C45 0 25 70 90 45.2 44.8 44.4 44.2 45.4 45.0 44.6 70mhz 20mhz 50mhz figure 12. snr vs. temperature, f s = 135 msps db t c C 8 c 46.0 44.0 C60 100 C40 C20 0 20 40 60 80 45.8 45.2 44.8 44.4 44.2 45.6 45.4 45.0 44.6 20mhz 50mhz 70mhz figure 13. snr vs. temperature, f s = 200 msps db encode pulsewidth C ns 50 30 0.0 8.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 48 42 38 34 32 46 44 40 36 f s = 135msps f in = 10.3mhz snr sinad figure 14. snr vs. cl ock pulsewidth, (t pwh ): f s = 135 msps
ad9054 C8C rev. 0 encode pulsewidth C ns db 50 38 30 0.0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 48 40 36 32 44 42 34 46 f s = 200msps f in = 10.3mhz snr sinad figure 15. snr vs. cl ock pulsewidth, (t pwh ): f s = 200 msps t c C 8 c db 46 38 C60 100 C40 C20 0 20 40 60 80 45 42 41 40 39 44 43 20mhz 50mhz 70mhz figure 16. sinad vs. temperature: f s = 135 msps t c C 8 c db 46 38 C60 100 C40 C20 0 20 40 60 80 45 42 41 40 39 44 43 20mhz 50mhz 70mhz figure 17. sinad vs. temperature: f s = 200 msps f s C msps dbc C70 C50 25 225 50 100 150 200 250 300 C68 C58 C56 C54 C52 C64 C60 C66 C62 C48 C46 75 125 175 270 3rd harmonic 2nd harmonic figure 18. harmonic distortion vs. f s :f in = 19.7 mhz f s C msps C60 0 25 300 50 100 150 225 270 75 125 175 200 250 C40 C20 C10 C50 C30 2nd harmonic 3rd harmonic figure 19. harmonic distortion vs. f s :f in = 70.1 mhz t c C 8 c db C40 C70 C60 100 C40 C20 0 20 40 60 80 C45 C50 C55 C60 C65 70mhz 50mhz 20mhz figure 20. 2nd harmonic vs. temperature: f s = 135 msps
ad9054 C9C rev. 0 t c C 8 c C40 C70 C60 100 C40 C20 0 20 40 60 80 C45 C50 C55 C60 C65 db 70mhz 50mhz 20mhz figure 21. 2nd harmonic vs. temperature: f s = 200 msps t c C 8 c C40 C70 C60 100 C40 C20 0 20 40 60 80 C45 C50 C55 C60 C65 db 70mhz 50mhz 20mhz figure 22. 3rd harmonic vs. temperature: f s = 135 msps t c C 8 c C40 C70 C60 100 C40 C20 0 20 40 60 80 C45 C50 C55 C60 C65 db 70mhz 50mhz 20mhz figure 23. 3rd harmonic vs. temperature: f s = 200 msps f in C mhz db 0 C3 C6 0 500 50 100 150 200 250 300 350 400 450 C1 C2 C4 C5 nyquist frequency 100mhz figure 24. frequency response: f s = 200 msps mhz db 0 100 10 20 30 40 50 60 70 80 90 0 C10 C90 C50 C60 C70 C80 C30 C40 C20 fundamental = C0.5dbfs snr = 45.8db sinad = 45.2db 2nd harmonic = 69.8db 3rd harmonic = 61.6db figure 25. spectrum: f s = 200 msps, f in = 19.7 mhz mhz db 0 100 10 20 30 40 50 60 70 80 90 0 C10 C90 C50 C60 C70 C80 C30 C40 C20 fundamental = C0.5dbfs snr = 44.6db sinad = 37.6db 2nd harmonic = C63.1db 3rd harmonic = C39.1db figure 26. spectrum: f s = 200 msps, f in = 70.1 mhz
ad9054 C10C rev. 0 db mhz 0 100 10 20 30 40 50 60 70 80 90 0 C10 C90 C50 C60 C70 C80 C30 C40 C20 C100 f1 = 55.0mhz f2 = 56.0mhz f1 = f2 = C7.0dbfs figure 27. two tone intermodulation distortion i oh C ma v oh C volts 5.0 2.0 0.0 0.0 C10.0 C1.0 C2.0 C3.0 C4.0 C5.0 C6.0 C7.0 C8.0 C9.0 4.5 2.5 1.5 0.5 3.5 3.0 1.0 4.0 figure 28. output voltage high vs. output current v ol C volts i ol C ma 1.0 0.0 0.0 8.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.9 0.6 0.4 0.2 0.1 0.8 0.7 0.5 0.3 figure 29. output voltage low vs. output current t c C 8 c ns 7 0 C60 100 C40 C20 0 20 40 60 80 6 4 3 2 1 5 t pd t v figure 30. output delay vs. temperature iref out C ma 2.55 2.48 2.45 C20 2 C18 C16 C14 C12 C10 C8 C6 C4 C2 0 2.54 2.49 2.47 2.46 2.53 2.51 2.52 2.50 vref out C volts figure 31. reference voltage vs. reference load v dd C volts vref out C volts 2.502 2.501 2.498 3.0 6.5 3.5 4.0 4.5 5.0 5.5 6.0 2.500 2.499 figure 32. reference voltage vs. power supply voltage
ad9054 C11C rev. 0 application notes theory of operation the ad9054 combines analog devices patented magamp bit- per-stage architecture with flash converter technology to create a high performance, low power adc. for ease of use the part includes an onboard reference and input logic that accepts ttl, cmos or pecl levels. the analog input signal is buffered by a high-speed differential amplifier and applied to a track-and-hold (t/h) circuit. this t/h captures the value of the input at the sampling instant and maintains it for the duration of the conversion. the sampling and conversion process is initiated by a rising edge on the encode input. once the signal is captured by the t/h, the four most significant bits (msbs) are sequentially encoded by the magamp string. the residue signal is then encoded by a flash comparator string to generate the four least significant bits (lsbs). the comparator outputs are decoded and com- bined into the eight-bit result. if the user has selected single channel mode ( demux = high), the eight-bit data word is directed to the channel a output bank. data are strobed to the output on the rising edge of the encode input with four pipeline delays. if the user has selected dual channel mode ( demux = low) the data are alternately directed between the a and b output banks and have five pipeline delays. at power-up, the n sample data can ap- pear at either the a or b port. to align the data in a known state the user must strobe data sync (ds, ds ) per the conditions described in the timing section. graphics applications the high bandwidth and low power of the ad9054 make it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another and is relatively stable for a period of time. examples of these include digitizing the output of com- puter graphic display systems and very high speed solid state imagers. these applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the a/d must settle and sample the input in well under one pixel time. the archi- tecture of the ad9054 is vastly superior to older flash architec- tures, which not only exhibit excessive input capacitance (which is very hard to drive) but can make major errors when fed a very rapidly slewing signal. the ad9054s extremely wide bandwidth track/hold circuit processes these signals without difficulty. using the ad9054 good high speed design practices must be followed when using the ad9054. to obtain maximum benefit, decoupling capaci- tors should be physically as close to the chip as possible. we recommend placing a 0.1 m f capacitor at each power-ground pin pair (9 total) for high frequency decoupling, and including one 10 m f capacitor for local low frequency decoupling. the vref in pin should also be decoupled by a 0.1 m f capacitor. the part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmis- sion line effects. this avoids the need for termination resistors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. we have obtained optimum performance on our evaluation board by tying all v dd pins to a quiet analog power supply system, and tying all gnd pins to a quiet analog system ground. minimum encode rate the minimum sampling rate for the ad9054 is 25 mhz. to achieve very high sampling rates, the track/hold circuit employs a very small hold capacitor. when operated below the minimum guaranteed sampling rate, the t/h droop becomes excessive. this is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. lower effective sampling rates may be easily supported by oper- ating the converter in dual port output mode and using only one output channel. a majority of the power dissipated by the ad9054 is static (not related to conversion rate) so the penalty for clock- ing at twice the desired rate is not high. reference the ad9054 internal reference, vref, provides a simple, cost effective reference for many applications. it exhibits reasonable accuracy and excellent stability over power supply and tempera- ture variations. the vref out pin can simply be strapped to the vref in pin. the internal reference can be used to drive additional loads (up to several ma), including multiple a/d con- verters as might be required in a triple video converter application. when an external reference is desired for accuracy or other requirements, the ad9054 should be driven directly by the external reference source connected to pin vref in (vref out can be left floating). the external reference can be set to 2.5 v 0.25 v. if vref in is raised by 10% (set to 2.75 v) the analog full-scale range will increase by 10% to 1.024 1.1 = 1.1264 v. the new input range will then be ain 0.5632 v. digital inputs snr performance is directly related to the sampling clock sta- bility in a/d converters, particularly for high input frequencies and wide bandwidths. a low jitter clock (<10 ps @ 100 mhz) is essential for optimum performance when digitizing signals that are not presampled. encode and data select (ds) can be driven differentially or single-ended. for single-ended operation, the complement inputs ( encode , ds ) are internally biased to v dd /3 (~1.5 v) by a high impedance on-chip resistor divider (figure 5), but they may be externally driven to establish an alternate threshold if desired. a 0.1 m f decoupling capacitor to ground is sufficient to maintain a threshold appropriate for ttl or cmos logic. t amb C 8 c vref out C volts 2.502 2.501 2.498 C40 100 C20 0 20 40 60 80 2.500 2.499 figure 33. reference voltage vs. temperature
ad9054 C12C rev. 0 when driven differentially, encode and ds will accommo- date differential signals centered between 1.5 v and 4.5 v with a total differential swing 3 800 mv (v id 3 400 mv). note the 6-diode clock input protection circuitry in figure 5. this limits the differential input voltage to ~ 2.1 v. when the diodes turn on, current is limited by the 300 w series resistor. exceeding 2.1 v across the differential inputs will have no im- pact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter. clock clock enc enc v ih d v ic m v il d clock enc enc v ih d v ic m v il d 0.1 m f v id v id a. driving differential inputs differentially b. driving differential inputs single-endedly figure 34. input signal level definitions single port mode when operated in a single port mode ( demux = high), the timing of the ad9054 is similar to any high speed a/d con- verter (figure 1). a sample is taken on every rising edge of encode, and the resulting data is produced on the output pins following the fourth rising edge of encode after the sample was taken (four pipeline delays). the output data are valid t pd after the rising edge of encode, and remain valid until at least t v after the next rising edge of encode. the maximum clock rate is specified as 100 msps. this is recommended because the guaranteed output data valid time equals the clock period (1/f s ) minus the output propagation delay (t pd ) plus the output valid time (t v ), which comes to 4.8 ns at 100 mhz. this is about as fast as standard logic is able to capture the data with reasonable design margins. the ad9054 will operate faster in single-channel mode if you are able to capture the data. when operating in single-channel mode, the outputs at port b are held static in a random state. figure 35 shows the ad9054 used in single-channel output mode. the analog input ( 0.5 v) is ac coupled and the encode input is driven by a ttl level signal. the chips internal refer- ence is used. vin 0.1 m f +5v 1k v 0.1 m f 0.1 m f nc clock vref out vref in ain ain demux ad9054 ds ds enc enc a port nc = no connect figure 35. single port modeac-coupled inputsingle- ended encode dual port mode in dual port mode ( demux = low), the conversion results are alternated between the two output ports (figure 2). this limits the data output rate at either port to 1/2 the conversion rate (encode), and supports conversion at up to 200 msps with ttl/cmos compatible interfaces. dual channel mode is required for guaranteed operation above 100 msps, but may be enabled at any specified conversion rate. the multiplexing is controlled internally via a clock divider, which introduces a degree of ambiguity in the port assignments. figure 2 illustrates that, prior to synchronization, either port a or port b may produce the even or odd samples. this is re- solved by exercising the data sync (ds) control, a differential input (identical to the encode input), which facilitates opera- tion at high speed. at least once after power-up, and prior to using the conversion data, the part needs to be synchronized by a falling edge (or a positive-going pulse) on ds (observing setup and hold times with respect to encode). if the converters internal timing is in conflict with the ds signal when it is exercised, then two data samples (one on each port) are corrupted as the converter is resynchronized. the converter then produces data with a known phase relationship from that point forward. note that if the converter is already properly synchronized, the ds pulse has no effect on the output data. this allows the con- verter to be continuously resynchronized by a pulse at 1/2 the encode rate. this signal is often available within a system, as it represents the master clock rate for the demultiplexed output data. of course, a single ds signal may be used to synchronize multiple a/d converters in a multichannel system. applications that call for the ad9054 to be synchronized at power-up or only periodically during calibration/reset (i.e., valid data is not required prior to synchronization), need only be concerned with the timing of the falling edge of ds. the falling edge of ds must satisfy the setup time defined by figure 2 and
ad9054 C13C rev. 0 the specification table. in this case the ds hold time specifica- tion on the rising edge can be ignored. applications that will continuously update the synchronization command need to treat the ds signal as a pulse and satisfy timing requirements on both rising and falling edges. it is easiest to consider the ds signal in this case to be a pulse train at one half the encode rate, the positive pulse nominally bracketing the encode falling edge on alternate cycles as shown in the tim- ing diagram (figure 2). the falling/rising edge of ds has to satisfy a minimum setup time (t sds ) before the rising/falling edge of encode; similarly, the rising/falling edge of ds has to satisfy a minimum hold time (t hds ) relative to the rising/falling edge of encode. ds can fall a minimum of t hds after encode falls and a maximum of t sds before the next encode rises. ds can rise a minimum of t hds after encode rises and a maximum of t sds before encode falls. this timing requirement produces a tight timing window at higher encode rates. synchronization by a single reset edge results in a simpler timing solution in many applications. for example, synchronization may be provided at the beginning of each graphics line or frame. the data are presented at the output of the ad9054 in a ping- pong (alternating) fashion to optimize the performance of the converter. it may be aligned for presentation as sixteen bits in parallel by adding a register stage to the output. in dual channel mode, the converted data is produced five clock cycles after the rising edge of encode on which the sample is taken (five pipeline delays). vin 0.1 m f 1k v 0.1 m f 0.1 m f nc clock vref out vref in ain ain demux ad9054 ds ds enc enc a port ds '573 b port '74 divide by 2 nc = no connect figure 36. dual port modealigned output data in figure 36, the converter is operating in dual port mode, with data coming alternately out of port a and port b. the figure illustrates how the output data may be aligned with an output latch to produce a 16-bit output at 1/2 the conversion clock rate. the data sync input must be properly exercised to time the a port with the synchronizing latch.
ad9054 C14C rev. 0 evaluation board the ad9054 evaluation board offers an easy way to test the ad9054. it provides dc biasing for the analog input, generates the latch clocks for both full speed and demuxed modes, and in- cludes a reconstruction dac. the board has several different modes of operation, and is shipped in the following configuration: dc-coupled analog input demuxed outputs differential clocks internal voltage reference. vref out vref in ain ain demux ad9054 ds ds enc enc a port '574 a port '574 dac clk a clk b clocking enc enc s102 vref ext s103 dc bias 50 v ain 5v d ff d c reset button clk a clk b s104 s105 enc 50 v enc 50 v figure 37. pcb block diagram analog input the evaluation board accepts a 1 v input signal centered at ground. the boards input circuitry then biases this signal to +2.5 v in one of two ways: 1. dc-coupled through an ad9631 op amp; this is the mode in which it is shipped. potentiometer r7 provides adjustment of the bias voltage. 2. ac-coupled through c1. these two modes are selected by jumpers s101 and s103. for dc coupling, the s101 jumper is connected between the two left pins and the s103 jumper is connected between the two lower pins. for ac coupling, the s101 jumper is connected between the two right pins and the s103 jumper is connected between the two upper pins. encode the ad9054 encode input can be driven two ways: 1. differential ttl, cmos, or pecl; it is shipped in this mode. 2. single-ended ttl or cmos. to use in this mode, remove r11, the 50 w chip resistor located next to the encode input, and insert a 0.1 m f ceramic capacitor into the c5 slot. c5 is located between the enc connector and the encode input to the dut and is marked on the back side of the board. in this mode, encode is biased with internal resis- tors to 1.5 v, but it can be externally driven to any dc voltage. voltage reference the ad9054 has an internal 2.5 v voltage reference. an exter- nal reference may be employed instead. the evaluation board is configured for the internal reference. to use an external refer- ence, connect it to the (vref) pin on the power connector and move jumper s102. single port mode single port mode sets the ad9054 to produce data on every clock cycle on output port a only. to test in this mode, jumper s104 should be set to single channel and s106 and s107 must be set to f (for full). the maximum speed in single port mode is 100 msps. dual port mode dual port or half speed output mode sets the adc to produce data alternately on port a and port b. in this mode, the reset function should be implemented. to test in this mode, set jumper s104 to dual channel, and set s106 and s107 to d (for dual port). the maximum speed in this mode is 200 msps. reset reset drives the ad9054s data sync (ds) pins. when oper ating in single port mode, reset is not used. in dual- channel mode it is needed for two reasons: to synchronize the timing of port a data and port b data with a known clock edge, as descri bed in the data sheet, and to synchr onize the evaluation boards latch clocks with the data coming out of the ad9054. reset can be driven in two ways: by pushing the reset button on the board, or externally, with a ttl pulse through connector j5 or j6. dac out the dac output is a representation of the data on output port a only. output port b is not reconstructed. troubleshooting if the board does not seem to be working correctly, try the fol- lowing: check that all jumpers are in the correct position for the desired mode of operation. push the reset button. this will align the 9054s data output with the half speed latch clocks. switch the jumper s105 from a-r to r-b or vice-versa, then push the reset button. in demuxed mode, this will have the effect of inverting the half speed latch clocks. at high encode rates, the evaluation boards clock generation circuitry is sensitive to the +5 v digital power supply. at high encode rates, the +5 v digital power should be kept below +5.2 v. this is an evaluation board sensitivity and not an ad9054 sensitivity. the ad9054 evaluation board is provided as a design example for customers of analog devices, inc. adi makes no warran- ties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
ad9054 C15C rev. 0 figure 38. evaluation board schematic gnd C5.2v 4 3 2 7 6 s1 q1 d1 q1 r1 5pb rp1 510 5 u6 10h131 2 1 3 s105 jumper 2 1 3 s107 jumper 2 1 3 s106 jumper 10h125 u7 10h125 u7 10h125 u7 10h125 u7 6 7 4 2 3 10 11 12 14 15 13 vref +5va C5.2v gnd +5v tb1 11 ad96685r u3 12 6 4 3 r11 49.9 v bnc j3 enc r10 49.9 v bnc j2 enc +5v 1 4 +5v 6 5 2 3 u2 74f74 pr q d q cl c +5va gnd gnd +5va gnd +5va +5va gnd +5va gnd 23 33 +5va gnd +5va gnd 11 22 21 20 19 18 17 16 15 14 13 12 vref in gnd vdd gnd ain ain gnd vdd ds db3 db2 db1 (lsb) db0 vdd gnd gnd vdd (lsb) da0 da1 da2 enc vref out gnd vdd vdd gnd vdd gnd db7 db6 db5 db4 vdd gnd vdd gnd da7 da6 da5 da4 da3 enc ua1 ad9054bst demux ds 2 1 3 s104 jumper gnd +5va r9 100 v gnd rst c4 0.1 m f +5v b1 button +5v 34 35 36 37 38 39 40 41 42 43 44 gnd +5va gnd gnd +5va c1 0.1 m f r12 1k v c36, c37, and r17-r20 not installed for standard operation 2 1 3 s103 jumper u1 ad9631r 2 3 2 1 3 s101 jumper 6 r4 140 v r2 140 v r1 49.9 v bnc j1 ain c2 0.1 m f c35 0.1 m f r7 1k v r5 10 v r8 2k v r6 2k v 2 1 3 s102 jumper c3 10 m f vref 1q 2q 3q 4q 5q 6q 7q 8q 12 13 14 15 16 17 18 19 oe u4 74f574dw c5 1d 2d 3d 4d 5d 6d 7d 8d 9 8 7 6 5 4 3 2 ck 11 1 12 13 14 15 16 17 18 19 u5 74f574dw 9 8 7 6 5 4 3 2 11 1 1 2 3 4 5 6 7 8 9 10 c9 10 m f c10 0.1 m f c11 0.1 m f c12 0.1 m f c13 0.1 m f c14 0.1 m f c15 0.1 m f c16 0.1 m f c17 0.1 m f c18 0.1 m f c19 0.1 m f c20 0.1 m f c21 0.1 m f c22 0.1 m f c28 0.1 m f +5v c8 0.1 m f r14 2k v c6 0.1 m f c7 0.1 m f +5v db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 27 24 23 19 18 17 16 15 dvdd avdd comp2 comp1 fsadj refio reflo sleep r15 49.9 v 21 22 a i out b 1 r3 100 v 1q 2q 3q 4q 5q 6q 7q 8q oe 1d 2d 3d 4d 5d 6d 7d 8d ck 28 5 +5v rst u8 ad9760ar gnd 11 10 9 8 7 6 5 4 1 12 h20sm j5 13 14 15 16 17 18 19 20 2 3 r21-r39 100 v r21 r39 c37 drpf j6 20 29 28 27 26 25 24 23 22 2 30 31 32 33 34 35 36 37 21 reset b8a b7a b6a b5a b4a b3a b2a b1a drb dra b1b b2b b3b b4b b5b b6b b7b b8b r16 49.9 v bnc j4 dac out vref +5v analog C5.2v ground +5v digital 1 2 3 4 5 c23 10 m f c24 0.1 m f c25 0.1 m f c26 0.1 m f c27 0.1 m f c29 0.1 m f +5va c30 10 m f c31 0.1 m f c32 0.1 m f c33 0.1 m f c34 0.1 m f C5.2v 1 2 3 4 5 6 clk
ad9054 C16C rev. 0 figure 39. assemblytop view figure 40. assemblybottom view figure 41. conductorstop view figure 42. conductorsbottom view
ad9054 C17C rev. 0 bill of materials gs00104 rev. b item qty part number reference description mfg/distributor 1 1 30 grm40z5u104m050bl c1, c2, c4, c6C8, 0.1 m f cer chip cap 0805 tti c10Cc22, c24Cc29, c31Cc35 1 2 1 p10fbk-nd r5 10 w surface mt res 1206 digi-key 1 3 21 p100fbk-nd r3, r9, r21Cr39 100 w surface mt res 1206 digi-key 1 4 4 t491c106m016as c3, c9, c23, c30 10 m f tantalum chip cap tti 1 5 2 p140fbk-nd r2, r4 140 w surface mt res 1206 digi-key 1 6 1 p1kfbk-nd r12 1 k w surface mt res 1206 digi-key 1 7 3 p2kfbk-nd r6, r8, r14 2 k w surface mt res 1206 digi-key 1 8 1 3296w-102-nd r7 1k trim pot top adj, 25 turn digi-key 1 9 1 k44-c37s-qj j6 37p d conn rt ang pcmt fem century elec 10 5 p49.9fbk-nd r1, r10, r11, 49.9 w surface mt res 1206 digi-key r15, r16 11 1 csc06a-01-511g rp1 510 w 6p bused res network tti 12 1 51f54113 tb1 8291z 3-pin terminal block newark 13 1 51f54112 tb1 8291z 2-pin terminal block newark 14 4 amp-227699-2 j1Cj4 bnc coax conn pcmt 5 lead time elec 15 1 mc10h131p u6 dip-16 dual d flip-flop hamilton/hallmark 16 1 mc10h125p u7 dip-16 quad ecl to ttl trans hamilton/hallmark 17 1 74f74sc-nd u2 so-14 fast ttl dual d flip-flop digi-key 18 1 tsw-120-08-g-s j5 header strip 20p gold male samtec alt: 1/2 90f3987 j5 40p header newark 19 1 ad96685br u3 high speed comp soic-16 analog devices, inc. 20 7 s90f9280 s101Cs107 shorting jumper newark 21 8 89f4700 s101Cs107, gnd 3-pin header (divide 1 of the newark 8 for 3 gnd holes) 22 2 mc74f574dw u4, u5 so-20 octal d type flip-flop hamilton/hallmark 23 1 ad9631ar u1 soic-8 op amp analog devices, inc. 24 1 ad9760ar u8 10-bit cmos dac soic-28 analog devices, inc. 25 1 ad9054st ua1 tqfp-44 dual 8-bit adc analog devices, inc. 26 1 p8002sct-nd b1 surface mount momentary digi-key pushbutton 27 4 90f1533 C bumpon protective bumper newark parts not on bill of materials, and not to be installed: c5, c36, c37, r17Cr20.
ad9054 C18C rev. 0 44-lead plastic thin quad flatpack (tqfp) (st-44) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) seating plane 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) outline dimensions dimensions shown in inches and (mm).
C19C
C20C c3146C8C10/97 printed in u.s.a.

▲Up To Search▲

Price & Availability of AD9054BST-135

	To Download AD9054BST-135 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .